The present invention generally relates to semiconductor devices, and in particular to master slice type integrated-circuit devices, which are capable of providing many kinds of logic circuits by carrying out desired interconnection for chips which are manufactured by common processes except a final interconnecting process. The present invention more particularly relates to improvements in input/output cells formed on chips in master slice type integrated-circuit devices such as a complementary metal oxide semiconductor gate array.
This type of semiconductor integrated-circuit device has a chip on which there are formed basic cells which are arranged in a matrix as well as input/output cells arranged around the basic cells. Each basic cell is generally composed of a plurality of transistors. The final interconnecting process has not yet been carried out for the basic cells. Therefore, desired logic circuits may be formed by interconnecting the transistors included in the basic cells. Input/output cells (hereafter referred to as I/O cells), which supply the logic circuits on the chip with signals from external circuits and/or feed output signals of the logic circuits to the external circuits, are arranged in peripheral regions on the chip. One I/O cell is generally made up of a protection circuit for absorbing over-voltage due to electrostatic discharge, a logic circuit having logic functions of an input buffer and/or an output buffer, and a bonding pad.
However, as will be described in detail later, the semiconductor devices aforementioned have disadvantages in that the number of I/O cells capable of being arranged in the chip peripheral regions is subject to some limitations and does not necessarily satisfy needs of customers. This is because all of the components forming the I/O cells are arranged in the peripheral regions on the chip, and therefore the size of each I/O cell is relatively large. In addition, it is difficult to arrange the I/O cells in regions on the chip very close to its corners, and to therefore utilize the chip corner regions efficiently. This leads to degradation in accuracy of a bonding process for connecting the bonding pads with corresponding lead patterns.